Unlike typical dynamic random access memory (DRAM), multivalue memory cells are configured to store one of four voltage levels per memory cell corresponding to four different data values represented logically by two bits of data storage (such as the binary values “00”, “01”, “10”, or “11”). Typical DRAM, by contrast, is configured to store one of two voltage levels corresponding to one bit of data storage (typically either a “1” or a “0”). U.S. Pat. No. 6,005,799 titled “METHODS AND CIRCUITS FOR SINGLE MEMORY DYNAMIC CELL MULTIVALUE DATA STORAGE” issued Dec. 21, 1999 discusses a multivalue dynamic random access memory (DRAM) device capable of sequential sensing of a stored voltage in a multivalue memory cell. Either the most significant bit (MSB) or the least significant bit (LSB) is sensed at a first step with the other bit sensed at a next step. These memory cells include a gating transistor and a storage element, such as a capacitor. Such sensing requires only two sense amplifiers, but sequential sensing imposes latency over concurrent sensing.
Concurrent sensing of multivalue bits using known techniques requires four sense amplifiers, each incorporating different reference voltages to sense the stored voltage. Such configurations include memory cells with one gating transistor and one capacitor coupled to a single bit line. Because all four sense amplifiers must use a different reference voltage, implementation and manufacturing of such sense amplifiers is complex.